Digital Logic (BIT152CO)
Number systems, binary arithmetic and codes, Boolean algebra, logic gates, gate-level minimization (K-Maps, Quine-McCluskey), combinational logic circuits (adders, subtractors, multiplexers, decoders, encoders, ALUs), synchronous and asynchronous sequential logic circuits (flip-flops, registers, counters), and semiconductor memories.
Unit 1: Number Systems and Codes5 hrs
- Digital systems overview and analog vs digital signals
- Binary, octal, decimal, and hexadecimal number systems and radix conversions
- Binary arithmetic: addition, subtraction, unsigned multiplication, and division
- Signed binary numbers: Signed magnitude, 1's complement, and 2's complement representations
- 2's complement arithmetic and hardware overflow detection conditions
- Binary codes: BCD (8421), Excess-3, Gray code, and ASCII alphanumeric code
- Code conversions: Binary to Gray code and Gray code to Binary conversion
- Error detecting and correcting codes: Parity bit generation and Hamming code principles
Unit 2: Boolean Algebra and Logic Gates6 hrs
- Basic definitions, axiomatic properties, and huntington postulates of Boolean algebra
- Fundamental theorems of Boolean algebra: Duality principle, involution, idempotency, and De Morgan's laws
- Boolean algebraic functions, truth tables, and algebraic manipulations
- Canonical and standard forms: Minterms, Maxterms, Sum of Products (SOP), and Product of Sums (POS)
- Digital logic gates: NOT, AND, OR, NAND, NOR, XOR, XNOR truth tables and symbols
- Universal logic gates: Implementation of inverter, AND, and OR gates using NAND-only and NOR-only logic
- Multi-level gate implementations and conversion to non-degenerate forms (AND-OR, NAND-NAND, NOR-NOR)
Unit 3: Simplification of Boolean Functions6 hrs
- The Map Method: Two-variable, three-variable, four-variable, and five-variable Karnaugh Maps (K-Maps)
- Adjacent squares, grouping rules (pairs, quads, octets), and algebraic minimization
- Prime implicants, essential prime implicants, and non-essential prime implicants
- Simplification with don't-care (X) conditions for incompletely specified functions
- Product of Sums (POS) simplification using K-Maps and duality
- Implementation of minimized expressions using two-level NAND and NOR logic
- Tabulation method (Quine-McCluskey method) for multi-variable boolean function optimization
Unit 4: Combinational Logic Circuits16 hrs
- Design procedure for combinational logic circuits: Problem specification, truth table, optimization, and schematic design
- Arithmetic circuits: Half adder, Full adder (circuit design and Boolean equations)
- Half subtractor and Full subtractor (circuit design using XOR and universal gates)
- Binary Parallel Adder (Ripple Carry Adder) and carry propagation delay analysis
- Carry Look-Ahead Adder (CLA) design: Carry generate (G) and carry propagate (P) expressions
- Binary adder-subtractor circuit using 2's complement and XOR control line
- Magnitude comparator: 1-bit and 4-bit binary magnitude comparators
- Decoders: 2-to-4 line decoder, 3-to-8 line decoder with enable inputs, and decoder tree expansion
- BCD-to-7-segment decoder/driver (common anode and common cathode displays)
- Encoders: Octal-to-binary encoder and 4-to-2/8-to-3 priority encoders
- Multiplexers (Data Selectors): 2-to-1, 4-to-1, 8-to-1 multiplexers and multiplexer expansion trees
- Implementation of arbitrary combinational Boolean logic functions using Multiplexers and Decoders
- Demultiplexers (Data Distributors) and decoder-demultiplexer duality
- Programmable logic devices: Read-Only Memory (ROM), Programmable Logic Array (PLA), and Programmable Array Logic (PAL)
Unit 5: Sequential Logic Circuits6 hrs
- Introduction to sequential circuits: Combinational vs sequential circuits, feedback, and memory
- Latches: SR latch using NOR gates and NAND gates, bistable multivibrator operation
- Clocked / Gated latches: Gated SR latch and Gated D latch (transparent latch)
- Flip-Flops: Clocked D flip-flop, Clocked JK flip-flop, and T (Toggle) flip-flop
- Race-around condition in level-triggered JK flip-flops and remedy using Master-Slave JK flip-flop architecture
- Edge-triggered flip-flops (positive and negative edge triggering)
- Characteristic tables, characteristic equations, and excitation tables of SR, D, JK, and T flip-flops
- Flip-flop conversion techniques (converting any flip-flop type to another)
- Clock skew, propagation delay, setup time, and hold time considerations
Unit 6: Registers and Counters6 hrs
- Registers: Basic buffer register with parallel load capability
- Shift registers: Serial-In Serial-Out (SISO), Serial-In Parallel-Out (SIPO), Parallel-In Serial-Out (PISO), Parallel-In Parallel-Out (PIPO)
- Bidirectional shift register with parallel load and Universal Shift Register architecture (IC 74194)
- Asynchronous (Ripple) counters: 4-bit binary ripple up-counter, down-counter, and propagation delay limitations
- Synchronous counters: 4-bit synchronous binary up-counter and up/down counter design
- Modulo-N counters: Decade (BCD) counter (IC 7490) and arbitrary truncated sequence counters
- Ring counter and Johnson (twisted ring / Mobius) counter
- Design procedure for synchronous sequential circuits: State diagrams, state tables, state reduction, state assignment, and flip-flop excitation derivation
Reference books
- M. Morris Mano and Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL (5th ed.), Pearson.
- Ronald J. Tocci, Neal S. Widmer, and Gregory L. Moss, Digital Systems: Principles and Applications (12th ed.), Pearson.
- Thomas L. Floyd, Digital Fundamentals (11th ed.), Pearson.
- Donald P. Leach, Albert Paul Malvino, and Goutam Saha, Digital Principles and Applications (8th ed.), McGraw-Hill.
- A. Anand Kumar, Fundamentals of Digital Circuits (4th ed.), PHI Learning.