Latches, Flip-Flops, Master-Slave Architecture & Excitation Tables
Idea in plain words
Latches are level-sensitive memory elements; Flip-flops are edge-triggered (synchronous clock transitions).
Exam tip
High-yield exam topic (Very High).
Explanation
Sequential circuits introduce feedback loops and bistable storage elements where the next state Q(t+1) depends on both the present inputs and present state Q(t). Characteristic equations express next-state logic: Q_{next} = S + R'Q (SR), Q_{next} = J Q' + K' Q (JK), Q_{next} = D (D), Q_{next} = T ⊕ Q (T). Excitation tables invert this relationship, determining required input excitations to drive a known transition from Q to Q_{next}.
Key points
- SR Flip-Flop: Set (S=1, R=0 => Q=1), Reset (S=0, R=1 => Q=0), No Change (S=0, R=0 => Q), Invalid state (S=1, R=1 => Q=Q'=0).
- JK Flip-Flop: Overcomes SR invalid state. J=1, K=1 produces Toggle (Q_{next} = Q').
- Race-Around Condition: Occurs in level-triggered JK flip-flops when clock pulse width t_p > propagation delay t_{pd}, causing multiple rapid toggles. Solved by Master-Slave JK architecture or Edge-Triggering.
- D Flip-Flop (Data/Delay): Q_{next} = D. Eliminates setup invalid states; foundation of shift registers.
- T Flip-Flop (Toggle): Q_{next} = T ⊕ Q. When T=1, state toggles; foundation of binary counters.
Example
Example
Master-Slave JK Flip-Flop: Composed of two cascaded clocked latches. The master responds to J and K inputs on the rising edge of the clock (CLK = 1) while the slave is isolated; on the falling edge (CLK = 0), the slave latches the master's state and updates the output Q.
Code examples
// Summary of Flip-Flop Excitation Requirements:
// Transition: Q(t) -> Q(t+1) | S R | J K | D | T
// ----------------------------|-------|--------|-----|----
// 0 -> 0 | 0 X | 0 X | 0 | 0
// 0 -> 1 | 1 0 | 1 X | 1 | 1
// 1 -> 0 | 0 1 | X 1 | 0 | 1
// 1 -> 1 | X 0 | X 0 | 1 | 0
// Conversion from JK Flip-Flop to D Flip-Flop:
// D is connected directly to J; D' (via NOT gate) is connected to K.
// Proof: Q_next = J*Q' + K'*Q = D*Q' + (D')'*Q = D*Q' + D*Q = D*(Q' + Q) = D. (Verified)
Exam questions
- [8 Marks] What is race-around condition in a JK flip-flop? Explain how it is eliminated in a Master-Slave JK flip-flop with circuit and timing diagrams.
- [7 Marks] Convert an SR Flip-Flop into a JK Flip-Flop. Show the excitation table, K-maps, and final logic schematic.
- [7 Marks] Derive the characteristic equations and excitation tables for JK, D, and T flip-flops.