Shift Registers, Universal Shift Registers, Ripple & Synchronous Counters
Idea in plain words
Registers are cascaded flip-flop arrays storing multi-bit binary words with common clock and control lines.
Exam tip
High-yield exam topic (Very High).
Explanation
Digital counters cycle through predefined sequences of binary states upon clock transitions. Synchronous counter design follows a systematic 5-step procedure: (1) state diagram, (2) state table with next-state assignments, (3) selection of flip-flop type and excitation derivation, (4) K-map minimization for flip-flop control inputs, and (5) circuit implementation.
Key points
- Shift Register Modes: SISO (Serial-In Serial-Out), SIPO (Serial-In Parallel-Out), PISO (Parallel-In Serial-Out), PIPO (Parallel-In Parallel-Out).
- Universal Shift Register (IC 74194): Features 4 operational modes controlled by S1, S0 (00: Locked/Hold, 01: Shift-Right, 10: Shift-Left, 11: Parallel Load).
- Asynchronous (Ripple) Counter: Output of flip-flop n serves as clock for flip-flop n+1. Simpler wiring, but accumulates propagation delay (t_{total} = N · t_{pd}), limiting maximum clock frequency.
- Synchronous Counter: All flip-flops trigger simultaneously from a master clock; next states are governed by combinational excitation gating, eliminating cumulative propagation delay.
- Modulo-N / Decade Counters: Truncates 2^N count sequence using NAND reset feedback when target count (e.g., 1010 for Decade counter) is reached.
Example
Example
Johnson Counter (Twisted Ring Counter): Connects the inverted output Q'_n of the last flip-flop to the data input D_0 of the first flip-flop. An n-flip-flop Johnson counter produces 2n unique states (e.g., 4 flip-flops yield 8 states), compared to n states in a simple Ring counter.
Code examples
// Systematic Design of a 3-Bit Synchronous Up-Counter Using T Flip-Flops:
// Count Sequence: 000 -> 001 -> 010 -> 011 -> 100 -> 101 -> 110 -> 111 -> 000
// Present State (Q2 Q1 Q0) | Next State (Q2+ Q1+ Q0+) | Excitations: T2 T1 T0
// 0 0 0 | 0 0 1 | 0 0 1
// 0 0 1 | 0 1 0 | 0 1 1
// 0 1 0 | 0 1 1 | 0 0 1
// 0 1 1 | 1 0 0 | 1 1 1
// 1 0 0 | 1 0 1 | 0 0 1
// 1 0 1 | 1 1 0 | 0 1 1
// 1 1 0 | 1 1 1 | 0 0 1
// 1 1 1 | 0 0 0 | 1 1 1
// Equations derived from K-maps:
// T0 = 1 (Toggles every clock cycle)
// T1 = Q0 (Toggles when Q0 = 1)
// T2 = Q1 · Q0 (Toggles when both Q1 and Q0 are 1)
Exam questions
- [8 Marks] Design a 3-bit Synchronous Binary Up/Down Counter using JK Flip-Flops with an external control line M (M=0 for UP, M=1 for DOWN).
- [7 Marks] Explain the internal architecture and operational modes of a 4-bit Universal Shift Register.
- [7 Marks] Differentiate between Synchronous and Asynchronous counters. Design a Mod-6 asynchronous counter using T flip-flops.